==== //depot/dev/AdvancedAccessories/PUB/src/kernel/linux-2.6.21-rimpub-eng-drop-1/arch/arm/mach-davinci/board-dm355-evm.c#1 - /va7400/home/rpau/perforce/rpau-linux-scm/dev/AdvancedAccessories/PUB/src/kernel/linux-2.6.21-rimpub-eng-drop-1/arch/arm/mach-davinci/board-dm355-evm.c ==== 29a30 > #include 50a52 > #include 59a62,71 > > //#define __MTD_MAKE_WRITEABLE__ // Placed here for testing only. This should be part of the regular build. > > > #if defined(__MTD_MAKE_WRITEABLE__) > #define MTD_PROTECTION_KEY 0 // Not write protected > #else > #define MTD_PROTECTION_KEY MTD_WRITEABLE // Write protected (Not intuitive however it masks the writable flag) > #endif //defined(__MTD_UNPROTECTED__) > 60a73,139 > * GPIO constants (RP 2009/05/28) > * - All contants are prefixed with "k_" to denote kernel, > * this is to differ them from definitions in pub.h > **************************************************************************/ > #define GIO(i_io) (i_io) > > #ifdef CONFIG_RIM_PUB > > #if defined(__EV1_1__) > #define k_NTSC_PAL GIO(0) //PAL/NTSC mode selection > #elif defined(__EV2__) > #define k_NOT_USED GIO(0) //not used > #endif > > #define k_BUTTON GIO(1) > #define k_SV_DET GIO(2) > #define k_VGA_DET GIO(3) > #define k_V_SEL GIO(4) > > #if defined(__EV1_1__) > #define k_WP_CTRL GIO(5) //NAND write protection > #elif defined(__EV2__) > #define k_NTSC_PAL GIO(5) //PAL/NTSC mode selection > #endif > #define GPIO_5 GIO(5) > > #define GPIO_PIN_SDA GIO(6) > #define GPIO_PIN_SCL GIO(7) > > #define GPIO_8 GIO(8) > #define GPIO_10 GIO(10) > #define GPIO_11 GIO(11) > > #define GPIO_31 GIO(31) > #define GPIO_34 GIO(34) > #define GPIO_35 GIO(35) > #define GPIO_36 GIO(36) > #define GPIO_37 GIO(37) > #define GPIO_54 GIO(54) > #define GPIO_55 GIO(55) > #define GPIO_56 GIO(56) > #define GPIO_57 GIO(57) > #define GPIO_58 GIO(58) > #define GPIO_59 GIO(59) > #define GPIO_60 GIO(60) > #define GPIO_61 GIO(61) > #define GPIO_71 GIO(71) > > #define k_VID_EN GIO(87) > > #if defined(__EV1_1__) > #define k_BT_EN GIO(93) > #endif > > #define k_BT_SHTD GIO(91) > #define k_BT_SHUTD_N GIO(91) > > #define k_BT_CR GIO(92) > #define k_CLK_REQ_OUT GIO(92) > > #define k_BT_RTS GIO(21) > #define k_UART2_CTS GIO(21) > > #endif > > > /************************************************************************** 89c168 < .uartclk = 24000000, --- > .uartclk = 107625000, 129c208,209 < /* bootloader (UBL, U-Boot, BBT) in sectors: 0 - 14 */ --- > /* RBL will look for UBL in page 0 of the first 24 blocks starting > * at block 1. We reserve block 1 to block 7 for redundant UBLs */ 131c211 < .name = "bootloader", --- > .name = "UBL", 133,134c213,221 < .size = 15*NAND_BLOCK_SIZE, < .mask_flags = MTD_WRITEABLE, /* force read-only */ --- > .size = 8 * NAND_BLOCK_SIZE, > .mask_flags = MTD_PROTECTION_KEY, /* force read-only in normal operation */ > }, > /* uBoot will be kept in block 8 to 14*/ > { > .name = "UBoot", > .offset = MTDPART_OFS_APPEND, > .size = 7 * NAND_BLOCK_SIZE, > .mask_flags = MTD_PROTECTION_KEY, /* force read-only in normal operation */ 136c223 < /* bootloader params in the next sector 15 */ --- > /* bootloader params in the next block 15 */ 140,141c227,228 < .size = 1*NAND_BLOCK_SIZE, < .mask_flags = MTD_WRITEABLE, /* force read-only */ --- > .size = NAND_BLOCK_SIZE, > .mask_flags = MTD_PROTECTION_KEY, /* force read-only in normal operation */ 143c230 < /* kernel in sectors: 16 */ --- > /* safemode kernel */ 145c232 < .name = "kernel", --- > .name = "safemode", 147,148c234,236 < .size = SZ_4M, < .mask_flags = 0 --- > .size = SZ_16M, > // .mask_flags = 0 > .mask_flags = MTD_PROTECTION_KEY, /* force read-only in normal operation */ 149a238 > /* normal mode kernel */ 151c240 < .name = "filesystem1", --- > .name = "kernel", 153c242 < .size = SZ_512M, --- > .size = SZ_16M, 156d244 < 158c246 < .name = "filesystem2", --- > .name = "filesystem", 211,219d298 < [2] = { /* < * Third (optional) memory resource is NAND I/O window < * for second NAND chip select < */ < .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16K, < .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16K + < SZ_16K - 1, < .flags = IORESOURCE_MEM, < }, 240c319 < __raw_writel(0x00000004, pinmux2); --- > __raw_writel(0x00000005, pinmux2); 381a461,477 > #if defined(CONFIG_RIM_PUB) > > static struct i2c_gpio_platform_data i2c_gpio_data = { > .sda_pin = GPIO_PIN_SDA, > .scl_pin = GPIO_PIN_SCL, > }; > > static struct platform_device i2c_gpio_device = { > .name = "i2c-gpio", > .id = 0, > .dev = { > .platform_data = &i2c_gpio_data, > }, > }; > > #endif > 395a492,494 > #if defined(CONFIG_RIM_PUB) > &i2c_gpio_device, > #endif 408c507 < [IRQ_DM355_VENCINT] = 6, --- > [IRQ_DM355_VENCINT] = 2, 410c509 < [IRQ_IMXINT] = 6, --- > [IRQ_IMXINT] = 7, 414c513 < [IRQ_DM355_UARTINT2] = 7, --- > [IRQ_DM355_UARTINT2] = 2, 440,441c539,540 < [IRQ_UARTINT0] = 3, < [IRQ_UARTINT1] = 3, --- > [IRQ_UARTINT0] = 7, > [IRQ_UARTINT1] = 7, 480a580,584 > > /* EDMA parameters adjustment to eliminate video noise.*/ > davinci_writel(0x00000004, 0x01c10140); > davinci_writel(0x00000004, 0x01c10540); > davinci_writel(0x00000011, 0x01c00284); 510a615,627 > case DAVINCI_LPSC_UART2: > /* set up Bluetooth related pinmux */ > davinci_cfg_reg(DM355_UART2_RTS); > davinci_cfg_reg(DM355_UART2_CTS); > davinci_cfg_reg(DM355_UART2_RXD); > davinci_cfg_reg(DM355_UART2_TXD); > davinci_cfg_reg(DM355_GPIO086_093); > break; > case DAVINCI_LPSC_GPIO: > /* GIO7 : ALT_SCL bit-banged i2c */ > davinci_cfg_reg(DM355_GPIO7); > break; > 551,553c668,670 < &serial_platform_data[kgdb8250_ttyS]); < kgdb8250_add_platform_port(kgdb8250_ttyS, < &serial_platform_data[kgdb8250_ttyS]); --- > &serial_platform_data[CONFIG_KGDB_PORT_NUM]); > kgdb8250_add_platform_port(CONFIG_KGDB_PORT_NUM, > &serial_platform_data[CONFIG_KGDB_PORT_NUM]); 560,574c677,691 < #if 0 // UBL should have this set already < davinci_cfg_reg(DM355_GPIO31); < davinci_cfg_reg(DM355_GPIO34); < davinci_cfg_reg(DM355_GPIO35); < davinci_cfg_reg(DM355_GPIO36); < davinci_cfg_reg(DM355_GPIO37); < davinci_cfg_reg(DM355_GPIO54); < davinci_cfg_reg(DM355_GPIO55); < davinci_cfg_reg(DM355_GPIO56); < davinci_cfg_reg(DM355_GPIO57); < davinci_cfg_reg(DM355_GPIO58); < davinci_cfg_reg(DM355_GPIO59); < davinci_cfg_reg(DM355_GPIO60); < davinci_cfg_reg(DM355_GPIO61); < davinci_cfg_reg(DM355_GPIO71); --- > int i; > > #if defined(__EV1_1__) > gpio_direction_input(k_NTSC_PAL); //PAL/NTSC mode selection > #elif defined(__EV2__) > gpio_direction_input(k_NOT_USED); //not used > #endif > gpio_direction_input(k_BUTTON); > gpio_direction_input(k_SV_DET); > gpio_direction_input(k_VGA_DET); > gpio_direction_output(k_V_SEL, 1); > #if defined(__EV1_1__) > gpio_direction_output(k_WP_CTRL, 1); //NAND write protection > #elif defined(__EV2__) > gpio_direction_input(k_NTSC_PAL); //PAL/NTSC mode selection 576,583c693,695 < gpio_direction_output(0, 0); < gpio_direction_output(1, 0); < gpio_direction_output(2, 0); < gpio_direction_output(4, 1); < gpio_direction_output(5, 1); /* FS455 reset */ < gpio_direction_output(8, 0); < gpio_direction_output(10, 0); < gpio_direction_output(11, 0); --- > gpio_direction_output(GPIO_8, 0); > gpio_direction_output(GPIO_10, 0); > gpio_direction_output(GPIO_11, 0); 585,597c697,709 < gpio_direction_output(31, 0); < gpio_direction_output(34, 1); < gpio_direction_output(35, 1); < gpio_direction_output(36, 1); < gpio_direction_output(37, 1); < gpio_direction_output(54, 1); < gpio_direction_output(55, 1); < gpio_direction_output(56, 0); < gpio_direction_output(57, 0); < gpio_direction_output(58, 0); < gpio_direction_output(59, 0); < gpio_direction_output(60, 0); < gpio_direction_output(61, 0); --- > gpio_direction_output(GPIO_31, 0); > gpio_direction_output(GPIO_34, 1); > gpio_direction_output(GPIO_35, 1); > gpio_direction_output(GPIO_36, 1); > gpio_direction_output(GPIO_37, 1); > gpio_direction_output(GPIO_54, 1); > gpio_direction_output(GPIO_55, 1); > gpio_direction_output(GPIO_56, 0); > gpio_direction_output(GPIO_57, 0); > gpio_direction_output(GPIO_58, 0); > gpio_direction_output(GPIO_59, 0); > gpio_direction_output(GPIO_60, 0); > gpio_direction_output(GPIO_61, 1); 599c711,746 < gpio_direction_output(71, 0); --- > gpio_direction_output(GPIO_71, 1); > > /* fix the pub boot up */ > gpio_direction_output(k_VID_EN, 1); > > /* Setup GPIO for the bluetooth XCVR */ > #if defined(__EV1_1__) > /* Drive BT_EN(93) high */ > gpio_direction_output(k_BT_EN, 1); > #endif > > /* Drive BT_SHUTD_N(91) high */ > gpio_direction_output(k_BT_SHUTD_N, 0); > > /* NSHUTD must assert low for a minimum of 10 milliseconds */ > mdelay(100); > > gpio_set_value(k_BT_SHUTD_N, 1); > > /* Poll CLK_REQ_OUT(92) it should be high */ > gpio_direction_input(k_CLK_REQ_OUT); > for (i = 0; i < 100; i++) { > mdelay(100); > if (gpio_get_value(k_CLK_REQ_OUT)) > break; > } > > /* Poll CLK_REQ_OUT(21) it should be low */ > gpio_direction_input(k_BT_RTS); > for (i = 0; i < 100; i++) { > mdelay(100); > if (!gpio_get_value(k_BT_RTS)) > return; > } > > printk(KERN_WARNING "WARNING: BT XCVR not ready\n"); 604c751 < gpio_set_value(5, 0); --- > gpio_set_value(GPIO_5, 0); 610c757 < gpio_set_value(5, 1); --- > gpio_set_value(GPIO_5, 1);