==== //depot/dev/AdvancedAccessories/PUB/src/kernel/linux-2.6.21-rimpub-eng-drop-1/drivers/media/video/davinci/fs455_encoder.c#1 - /va7400/home/rpau/perforce/rpau-linux-scm/dev/AdvancedAccessories/PUB/src/kernel/linux-2.6.21-rimpub-eng-drop-1/drivers/media/video/davinci/fs455_encoder.c ==== 4c4,8 < * Copyright (C) 2008 Montavista Inc. --- > * This driver has been heavily borrowed from THS8200_encoder device driver > * done by Texas Instrument Inc. This file is licensed under > * the terms of the GNU General Public License version 2. This program > * is licensed "as is" without any warranty of any kind, whether express > * or implied. 6,21d9 < * This program is free software; you can redistribute it and/or modify < * it under the terms of the GNU General Public License as published by < * the Free Software Foundation; either version 2 of the License, or < * (at your option) any later version. < * < * This program is distributed in the hope that it will be useful, < * but WITHOUT ANY WARRANTY; without even the implied warranty of < * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the < * GNU General Public License for more details. < * < * You should have received a copy of the GNU General Public License < * along with this program; if not, write to the Free Software < * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. < * < * This driver has been heavily borrowed from THS8200_encoder device driver < * done by Texas Instrument Inc. 31c19,172 < #include --- > #include > > #define DRIVER_AUTHOR "Santosh Shukla " > #define DRIVER_DESC "Focus FS455 video encoder driver" > > /* Kernel Header files */ > #include > #include > #include > /* encoder standard related strctures */ > #define FS455_MAX_NO_OUTPUTS (1) > #define FS455_LCD_NUM_STD (7) > #define FS455_MAX_NUM_STD (7) > #define FS455_STANDARD_INFO_SIZE FS455_LCD_NUM_STD > > enum fs455_i2_devices { > FS455, > }; > struct fs455_std_info { > int reg; > u32 val; > }; > struct fs455_params { > int outindex; > char *mode; > }; > struct fs455_config { > int no_of_outputs; > struct { > char *output_name; > int no_of_standard; > char *standards[FS455_MAX_NUM_STD]; > struct fs455_std_info *std_info; > } output[FS455_MAX_NO_OUTPUTS]; > }; > struct fs455_i2c_client { > struct i2c_client client; > u8 i2c_addr; > }; > > #define FS455_MAX_I2C_DEVICES 1 > struct fs455_channel { > struct vid_encoder_device *enc_device; > struct { > struct i2c_driver driver; > struct fs455_i2c_client clients[FS455_MAX_I2C_DEVICES]; > int i2c_registration; > } i2c_dev; > struct fs455_params params; > }; > > #define FS455_I2C_ADDR 0x4A > > /*! > * * FS455 register file > * */ > #define FS455_IHO 0x00 /*! Input Horizontal Offset */ > #define FS455_IVO 0x02 /*! Input Vertical Offset */ > #define FS455_IHW 0x04 /*! Input Horizontal Width */ > #define FS455_VSC 0x06 /*! Vertical Scaling Coefficient */ > #define FS455_HSC 0x08 /*! Horizontal Scaling Coefficient */ > #define FS455_BYPASS 0x0A /*! BYPASS */ > #define FS455_CR 0x0C /*! Command Register */ > #define FS455_MISC 0x0E /*! Miscellaneous Bits Register */ > #define FS455_NCON 0x10 /*! Numerator of NCO Word */ > #define FS455_NCOD 0x14 /*! Denominator of NCO Word */ > #define FS455_PLL_M_PUMP 0x18 /*! PLL M and Pump Control */ > #define FS455_PLL_N 0x1A /*! PLL N */ > #define FS455_PLL_PDIV 0x1C /*! PLL Post-Divider */ > #define FS455_SHP 0x24 /*! Sharpness Filter */ > #define FS455_FLK 0x26 /*! Filcker Filter Coefficient */ > #define FS455_GPIO 0x28 /*! General Purpose I/O, Output Enab */ > #define FS455_ID 0x32 /*! Part Identification Number */ > #define FS455_STATUS 0x34 /*! Status Port */ > #define FS455_FIFO_SP 0x36 /*! FIFO Status Port Fill/Underrun */ > #define FS455_FIFO_LAT 0x38 /*! FIFO Latency */ > #define FS455_CHR_FREQ 0x40 /*! Chroma Subcarrier Frequency */ > #define FS455_CHR_PHASE 0x44 /*! Chroma Phase */ > #define FS455_MISC_45 0x45 /*! Miscellaneous Bits Register 45 */ > #define FS455_MISC_46 0x46 /*! Miscellaneous Bits Register 46 */ > #define FS455_MISC_47 0x47 /*! Miscellaneous Bits Register 47 */ > #define FS455_HSYNC_WID 0x48 /*! HSync Width */ > #define FS455_BURST_WID 0x49 /*! Burst Width */ > #define FS455_BPORCH 0x4A /*! Back Porch Width */ > #define FS455_CB_BURST 0x4B /*! Cb Burst Amplitude */ > #define FS455_CR_BURST 0x4C /*! Cr Burst Amplitude */ > #define FS455_MISC_4D 0x4D /*! Miscellaneous Bits Register 4D */ > #define FS455_BLACK_LVL 0x4E /*! Black Level */ > #define FS455_BLANK_LVL 0x50 /*! Blank Level */ > #define FS455_NUM_LINES 0x57 /*! Number of Lines */ > #define FS455_WHITE_LVL 0x5E /*! White Level */ > #define FS455_CB_GAIN 0x60 /*! Cb Color Saturation */ > #define FS455_CR_GAIN 0x62 /*! Cr Color Saturation */ > #define FS455_TINT 0x65 /*! Tint */ > #define FS455_BR_WAY 0x69 /*! Width of Breezeway */ > #define FS455_FR_PORCH 0x6C /*! Front Porch */ > #define FS455_NUM_PIXELS 0x71 /*! Total num. of luma/chroma Pixels */ > #define FS455_1ST_LINE 0x73 /*! First Video Line */ > #define FS455_MISC_74 0x74 /*! Miscellaneous Bits Register 74 */ > #define FS455_SYNC_LVL 0x75 /*! Sync Level */ > #define FS455_VBI_BL_LVL 0x7C /*! VBI Blank Level */ > #define FS455_SOFT_RST 0x7E /*! Encoder Soft Reset */ > #define FS455_ENC_VER 0x7F /*! Encoder Version */ > #define FS455_WSS_CONFIG 0x80 /*! WSS Configuration Register */ > #define FS455_WSS_CLK 0x81 /*! WSS Clock */ > #define FS455_WSS_DATAF1 0x83 /*! WSS Data Field 1 */ > #define FS455_WSS_DATAF0 0x86 /*! WSS Data Field 0 */ > #define FS455_WSS_LNF1 0x89 /*! WSS Line Number Field 1 */ > #define FS455_WSS_LNF0 0x8A /*! WSS Line Number Field 0 */ > #define FS455_WSS_LVL 0x8B /*! WSS Level */ > #define FS455_MISC_8D 0x8D /*! Miscellaneous Bits Register 8D */ > #define FS455_VID_CNTL0 0x92 /*! Video Control 0 */ > #define FS455_HD_FP_SYNC 0x94 /*! Horiz. Front Porch & HSync Width */ > #define FS455_HD_YOFF_BP 0x96 /*! HDTV Lum. Offset & Back Porch */ > #define FS455_SYNC_DL 0x98 /*! Sync Delay Value */ > #define FS455_LD_DET 0x9C /*! DAC Load Detect */ > #define FS455_DAC_CNTL 0x9E /*! DAC Control */ > #define FS455_PWR_MGNT 0xA0 /*! Power Management */ > #define FS455_RED_MTX 0xA2 /*! RGB to YCrCb Matrix Red Coeff. */ > #define FS455_GRN_MTX 0xA4 /*! RGB to YCrCb Matrix Green Coeff. */ > #define FS455_BLU_MTX 0xA6 /*! RGB to YCrCb Matrix Blue Coeff. */ > #define FS455_RED_SCL 0xA8 /*! RGB to YCrCb Scaling Red Coeff. */ > #define FS455_GRN_SCL 0xAA /*! RGB to YCrCb Scaling Green Coeff. */ > #define FS455_BLU_SCL 0xAC /*! RGB to YCrCb Scaling Blue Coeff. */ > #define FS455_CC_FIELD_1 0xAE /*! Closed Caption Field 1 Data */ > #define FS455_CC_FIELD_2 0xB0 /*! Closed Caption Field 2 Data */ > #define FS455_CC_CONTROL 0xB2 /*! Closed Caption Control */ > #define FS455_CC_BLANK_VALUE 0xB4 /*! Closed Caption Blanking Value */ > #define FS455_CC_BLANK_SAMPLE 0xB6 /*! Closed Caption Blanking Sample */ > #define FS455_HACT_ST 0xB8 /*! HDTV Horizontal Active Start */ > #define FS455_HACT_WD 0xBA /*! HDTV Horizontal Active Width */ > #define FS455_VACT_ST 0xBC /*! HDTV Veritical Active Width */ > #define FS455_VACT_HT 0xBE /*! HDTV Veritical Active Height */ > #define FS455_PR_PB_SCALING 0xC0 /*! Pr and Pb Relative Scaling */ > #define FS455_LUMA_BANDWIDTH 0xC2 /*! Luminance Frequency Response */ > #define FS455_QPR 0xC4 /*! Quick Program Register */ > > /*! Command register bits */ > > #define CR_GCC_CK_LVL 0x2000 /*! Graphics Controller switching lev */ > #define CR_P656_LVL 0x1000 /*! Pixel Port Output switching level */ > #define CR_P656_IN 0x0800 /*! Pixel Port In */ > #define CR_P656_OUT 0x0400 /*! Pixel Port Out */ > #define CR_CBAR_480P 0x0200 /*! 480P Color Bars */ > #define CR_PAL_NTSCIN 0x0100 /*! PAL or NTSC input */ > #define CR_SYNC_MS 0x0080 /*! Sync Master or Slave */ > #define CR_FIFO_CLR 0x0040 /*! FIFO Clear */ > #define CR_CACQ_CLR 0x0020 /*! CACQ Clear */ > #define CR_CDEC_BP 0x0010 /*! Chroma Decimator Bypass */ > #define CR_NCO_EN 0x0002 /*! Enable NCO Latch */ > #define CR_SRESET 0x0001 /*! Soft Reset */ > > /*! Chip ID register bits */ > #define FS455_CHIP_ID 0xFE05 /*! Chip ID register expected value */ 38c179 < struct vid_encoder_device *enc); --- > struct vid_encoder_device *enc); 40c181,184 < struct vid_encoder_device *enc); --- > struct vid_encoder_device *enc); > > static int fs455_setcontrol(enum vid_enc_ctrl_id ctrl, unsigned char val, struct vid_encoder_device *enc); > static int fs455_getcontrol(enum vid_enc_ctrl_id ctrl, unsigned char *val, struct vid_encoder_device *enc); 45c189 < char *output, struct vid_encoder_device *enc); --- > char *output, struct vid_encoder_device *enc); 49c193 < u32 len); --- > u32 len); 51c195 < u32 len); --- > u32 len); 54,55c198,199 < struct i2c_driver *, < struct i2c_adapter *, int); --- > struct i2c_driver *, > struct i2c_adapter *, int); 64,65c208,272 < static struct vid_enc_mode_info < fs455_component_standards[FS455_LCD_NUM_STD] = { --- > static struct vid_enc_mode_info fs455_component_standards[FS455_LCD_NUM_STD] = { > { > .name = VID_ENC_STD_1024x768_60, > .std = 1, > .if_type = VID_ENC_IF_PRGB, > .interlaced = 0, > .xres = 1024, > .yres = 768, > .fps = {60, 1}, > .left_margin = 296, > .right_margin = 24, > .upper_margin = 35, > .lower_margin = 3, > .hsync_len = 136, > .vsync_len = 6, > .flags = 1 > }, > { > .name = VID_ENC_STD_1024x768_70, > .std = 1, > .if_type = VID_ENC_IF_PRGB, > .interlaced = 0, > .xres = 1024, > .yres = 768, > .fps = {60, 1}, > .left_margin = 280, > .right_margin = 24, > .upper_margin = 35, > .lower_margin = 3, > .hsync_len = 136, > .vsync_len = 6, > .flags = 1 > }, > { > .name = VID_ENC_STD_640x480_60, > .std = 1, > .if_type = VID_ENC_IF_PRGB, > .interlaced = 0, > .xres = 640, > .yres = 480, > .fps = {60, 1}, > .left_margin = 144, > .right_margin = 16, > .upper_margin = 35, > .lower_margin = 10, > .hsync_len = 96, > .vsync_len = 2, > .flags = 0 > }, > { > .name = VID_ENC_STD_800x600_60, > .std = 1, > .if_type = VID_ENC_IF_PRGB, > .interlaced = 0, > .xres = 800, > .yres = 600, > .fps = {60, 1}, > .left_margin = 216, > .right_margin = 40, > .upper_margin = 27, > .lower_margin = 1, > .hsync_len = 128, > .vsync_len = 4, > .flags = 0 > }, 67,80c274,288 < .name = VID_ENC_STD_1024x768, < .std = 1, < .if_type = VID_ENC_IF_PRGB, < .interlaced = 0, < .xres = 1024, < .yres = 768, < .fps = {60, 1}, < .left_margin = 235, < .right_margin = 69, < .upper_margin = 35, < .lower_margin = 2, < .hsync_len = 136, < .vsync_len = 1, < .flags = 1}, --- > .name = VID_ENC_STD_800x600_56, > .std = 1, > .if_type = VID_ENC_IF_PRGB, > .interlaced = 0, > .xres = 800, > .yres = 600, > .fps = {60, 1}, > .left_margin = 200, > .right_margin = 24, > .upper_margin = 24, > .lower_margin = 1, > .hsync_len = 72, > .vsync_len = 2, > .flags = 0 > }, 82,95c290,304 < .name = VID_ENC_STD_640x480, < .std = 1, < .if_type = VID_ENC_IF_PRGB, < .interlaced = 0, < .xres = 640, < .yres = 480, < .fps = {60, 1}, < .left_margin = 99, < .right_margin = 61, < .upper_margin = 35, < .lower_margin = 9, < .hsync_len = 96, < .vsync_len = 2, < .flags = 0}, --- > .name = VID_ENC_STD_NTSC_PRGB, > .std = 1, > .if_type = VID_ENC_IF_PRGB, > .interlaced = 0, > .xres = 1024, > .yres = 768, > .fps = {60, 1}, > .left_margin = 140, > .right_margin = 36, > .upper_margin = 59, > .lower_margin = 53, > .hsync_len = 100, > .vsync_len = 6, > .flags = 0 > }, 97,110c306,320 < .name = VID_ENC_STD_800x600, < .std = 1, < .if_type = VID_ENC_IF_PRGB, < .interlaced = 0, < .xres = 800, < .yres = 600, < .fps = {60, 1}, < .left_margin = 99, < .right_margin = 61, < .upper_margin = 35, < .lower_margin = 9, < .hsync_len = 96, < .vsync_len = 2, < .flags = 0}, --- > .name = VID_ENC_STD_PAL_PRGB, > .std = 1, > .if_type = VID_ENC_IF_PRGB, > .interlaced = 0, > .xres = 1024, > .yres = 768, > .fps = {60, 1}, > .left_margin = 150, > .right_margin = 66, > .upper_margin = 46, > .lower_margin = 26, > .hsync_len = 100, > .vsync_len = 6, > .flags = 0 > }, 113d322 < 116c325,326 < /* Mode specifc Focus chip register lookup table, used --- > /* > * Mode specifc Focus chip register lookup table, used 121,124c331,351 < fs455_component_std_info[FS455_LCD_NUM_STD][FS455_MAX_REGISTERS] < = { < {/* Focus Reg settings for 1024x768 mode */ < {FS455_QPR, 0x9c30}, --- > fs455_component_std_info[FS455_LCD_NUM_STD][FS455_MAX_REGISTERS] = { > {/* Focus Reg settings for 1024x768@60Hz mode */ > {FS455_CR, 0x2001}, > {FS455_CR, 0x2000}, > {FS455_QPR, 0x9C30}, > {FS455_DAC_CNTL, 0x00E1}, > {FS455_DAC_CNTL, 0x00E1}, > {FS455_VID_CNTL0, 0x0F06}, > {FS455_PLL_M_PUMP, 0x2617}, > {FS455_PLL_N, 0x00D7}, > {FS455_PLL_PDIV, 0x0202}, > {FS455_PWR_MGNT, 0x0408}, > {FS455_BYPASS, 0x0000}, > {FS455_CR, 0x2003}, > {FS455_CR, 0x2000}, > {-1, 0}, > }, > {/* Focus Reg settings for 1024x768@70Hz mode */ > {FS455_CR, 0x2001}, > {FS455_CR, 0x2000}, > {FS455_QPR, 0x9C30}, 131c358,365 < {FS455_CR, 0x2002}, --- > {FS455_PWR_MGNT, 0x0408}, > {FS455_BYPASS, 0x0000}, > {FS455_CR, 0x2003}, > {FS455_CR, 0x2000}, > {-1, 0}, > }, > {/* Focus Reg settings for 640x480@60Hz mode */ > {FS455_CR, 0x2001}, 132a367,374 > {FS455_QPR, 0x9C30}, > {FS455_DAC_CNTL, 0x00E1}, > {FS455_DAC_CNTL, 0x00E1}, > {FS455_VID_CNTL0, 0x0F06}, > {FS455_PLL_M_PUMP, 0x43DE}, > {FS455_PLL_N, 0x0086}, > {FS455_PLL_PDIV, 0x0707}, > {FS455_PWR_MGNT, 0x0408}, 134c376,378 < {0, 0}, --- > {FS455_CR, 0x2003}, > {FS455_CR, 0x2000}, > {-1, 0} 136,137c380,383 < { // Focus Reg settings for 640x480 mode < {FS455_QPR, 0x9c30}, --- > {/* Focus Reg settings for 800x600@60Hz mode */ > {FS455_CR, 0x2001}, > {FS455_CR, 0x2000}, > {FS455_QPR, 0x9C30}, 141,144c387,392 < {FS455_PLL_M_PUMP, 0x330F}, < {FS455_PLL_N, 0x008E}, < {FS455_PLL_PDIV, 0x0505}, < {FS455_CR, 0x2002}, --- > {FS455_PLL_M_PUMP, 0x3247}, > {FS455_PLL_N, 0x0086}, > {FS455_PLL_PDIV, 0x0202}, > {FS455_PWR_MGNT, 0x0408}, > {FS455_BYPASS, 0x0000}, > {FS455_CR, 0x2003}, 146,147c394 < {FS455_BYPASS, 0x0000}, < {0, 0} --- > {-1, 0} 149,150c396,399 < { // Focus Reg settings for 800x600 mode < {FS455_QPR, 0x9c30}, --- > {/* Focus Reg settings for 800x600@56Hz mode */ > {FS455_CR, 0x2001}, > {FS455_CR, 0x2000}, > {FS455_QPR, 0x9C30}, 154,156c403,434 < {FS455_PLL_M_PUMP, 0x330F}, < {FS455_PLL_N, 0x008E}, < {FS455_PLL_PDIV, 0x0505}, --- > {FS455_PLL_M_PUMP, 0x22BF}, > {FS455_PLL_N, 0x0086}, > {FS455_PLL_PDIV, 0x0303}, > {FS455_PWR_MGNT, 0x0408}, > {FS455_BYPASS, 0x0000}, > {FS455_CR, 0x2003}, > {FS455_CR, 0x2000}, > {-1, 0} > }, > {/* Focus Reg settings for NTSC mode, */ > {FS455_CR, 0x2001}, > {FS455_CR, 0x2000}, > {FS455_QPR, 0x9C46}, > #if defined(__EV1_1__) > {FS455_DAC_CNTL, 0x0001}, > {FS455_DAC_CNTL, 0x0001}, > #elif defined(__EV2__) > {FS455_DAC_CNTL, 0x00E4}, > {FS455_DAC_CNTL, 0x00E4}, > #endif > {FS455_VID_CNTL0, 0x0F00}, > {FS455_PLL_M_PUMP, 0x34EF}, > {FS455_PLL_N, 0x00B5}, > {FS455_PLL_PDIV, 0x0205}, > {FS455_PWR_MGNT, 0x0208}, > {FS455_VSC, 0x98BA}, > {FS455_HSC, 0x2B00}, > {FS455_IHO, 0x003B}, > {FS455_IVO, 0x0026}, > {FS455_SHP, 0x0008}, > {FS455_FLK, 0x000F}, > {FS455_LUMA_BANDWIDTH, 0x00F0}, 158a437,468 > {FS455_MISC, 0x0083}, > {FS455_MISC, 0x0483}, > {FS455_BYPASS, 0x0000}, > {-1, 0} > }, > {/* Focus Reg settings for PAL mode, */ > {FS455_CR, 0x2001}, > {FS455_CR, 0x2000}, > {FS455_QPR, 0x9C47}, > #if defined(__EV1_1__) > {FS455_DAC_CNTL, 0x0001}, > {FS455_DAC_CNTL, 0x0001}, > #elif defined(__EV2__) > {FS455_DAC_CNTL, 0x00E4}, > {FS455_DAC_CNTL, 0x00E4}, > #endif > {FS455_VID_CNTL0, 0x0F00}, > {FS455_PLL_M_PUMP, 0x36B7}, > {FS455_PLL_N, 0x00E0}, > {FS455_PLL_PDIV, 0x0307}, > {FS455_PWR_MGNT, 0x0208}, > {FS455_VSC, 0xBE7A}, > {FS455_HSC, 0x2B00}, > {FS455_IHO, 0x003D}, > {FS455_IVO, 0x002B}, > {FS455_SHP, 0x0008}, > {FS455_FLK, 0x000F}, > {FS455_LUMA_BANDWIDTH, 0xF0}, > {FS455_CR, 0x2102}, > {FS455_CR, 0x2100}, > {FS455_MISC, 0x0083}, > {FS455_MISC, 0x0483}, 160,161c470,471 < {0, 0} < } --- > {-1, 0} > }, 165d474 < 167,177c476,489 < .no_of_outputs = FS455_MAX_NO_OUTPUTS, < .output[0] = { < .output_name = VID_ENC_OUTPUT_LCD1, < .no_of_standard = FS455_LCD_NUM_STD, < .standards = { < VID_ENC_STD_1024x768, < VID_ENC_STD_640x480, < VID_ENC_STD_800x600 < }, < .std_info = (struct fs455_std_info *) < &fs455_component_std_info, --- > .no_of_outputs = FS455_MAX_NO_OUTPUTS, > .output[0] = { > .output_name = VID_ENC_OUTPUT_LCD_PRGB, > .no_of_standard = FS455_LCD_NUM_STD, > .standards = { > VID_ENC_STD_1024x768_60, > VID_ENC_STD_1024x768_70, > VID_ENC_STD_640x480_60, > VID_ENC_STD_800x600_60, > VID_ENC_STD_800x600_56, > VID_ENC_STD_NTSC_PRGB, > VID_ENC_STD_PAL_PRGB}, > .std_info = (struct fs455_std_info *) > &fs455_component_std_info, 182,187c494,500 < .params.outindex = 0, < .params.mode = VID_ENC_STD_1024x768, < .i2c_dev.clients[0] = { < .i2c_addr = FS455_I2C_ADDR < }, < .enc_device = NULL --- > .params.outindex = 0, > .params.mode = VID_ENC_STD_1024x768_60, > .i2c_dev.clients[0] = { > .i2c_addr = FS455_I2C_ADDR > }, > .i2c_dev.i2c_registration = 0, > .enc_device = NULL 198a512 > 208a523,527 > static struct vid_enc_control_ops fs455_control_ops = { > .setcontrol = fs455_setcontrol, > .getcontrol = fs455_getcontrol, > }; > 215c534 < .ctrl_ops = NULL, --- > .ctrl_ops = &fs455_control_ops, 218c537 < .misc_ops = &fs455_miscs_ops, --- > .misc_ops = NULL, 220a540,543 > #define MUTE_USER 1 //USER MUTE > #define MUTE_ERROR 2 //MUTE DUE TO CONNECTION ERROR > #define MUTE_OTHERS 4 //MUTE DUE TO OTHER REASONS > static unsigned char muteState; 221a545,548 > static unsigned char fs455RegAddr; > static unsigned char fs455RegH; > static unsigned char fs455RegL; > 223,224c550,580 < {/* currently used a stub */ < return 0; --- > { > int err = 0; > struct i2c_client *ch_client; > u16 reg, val; > u8 u8val; > > #if 0 > printk(KERN_INFO "\n%s FS455 DAC.\n", (flag==0) ? "Disable" : "Enable"); > if (enc == NULL) { > dev_err(fs455_i2c_dev, "NULL Pointer\n"); > return -EINVAL; > } > > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_PWR_MGNT, &val, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_PWR_MGNT failed (0x%x)\n", err); > return -EINVAL; > } > //printk(KERN_INFO "FS455_PWR_MGNT: 0x%x\n", val); > if(flag == 1){ > val &= 0xFF08; > err = fs455_i2c_write_reg(ch_client, FS455_PWR_MGNT, val, 2); > }else if(flag == 0){ > val |= 0x0007; > err = fs455_i2c_write_reg(ch_client, FS455_PWR_MGNT, val, 2); > }else{ > err = -EINVAL; > } > #endif > return err; 234c590 < #define BYTE (1) --- > #define BYTE (1) 240c596 < u32 len) --- > u32 len) 245c601 < *val = i2c_smbus_read_word_data(client, reg); --- > *(u16 *)val = i2c_smbus_read_word_data(client, reg); 248,249c604 < *((u16 *) val + 1) = < i2c_smbus_read_word_data(client, reg + 2); --- > *((u16 *) val + 1) = i2c_smbus_read_word_data(client, reg + 2); 253,254c608 < return 0; < --- > return 0; 259c613 < u32 len) --- > u32 len) 267c621 < (u8 *) & val); --- > (u8 *) &val); 273d626 < 276c629,630 < /* This function is called by the davinci_enc_mgr to initialise Focus encoder. --- > /* > * This function is called by the davinci_enc_mgr to initialise Focus encoder. 286c640 < if (NULL == enc) { --- > if (enc == NULL) { 298c652 < --- > fs455_channel_info.i2c_dev.i2c_registration |= 1; 307,308c661 < dev_err(fs455_i2c_dev, < "Error occured in setoutput\n"); --- > dev_err(fs455_i2c_dev, "Error occured in setoutput\n"); 312a666,670 > muteState = 0; > fs455RegAddr=0x32; > fs455RegH=0xFE; > fs455RegL=0x05; > fs455_channel_info.i2c_dev.i2c_registration |= 2; 322c680 < if (NULL == enc) { --- > if (enc == NULL) { 330,333c688,973 < i2c_del_driver(&fs455_channel_info.i2c_dev.driver); < for (i = 0; i < FS455_MAX_I2C_DEVICES; i++) { < fs455_channel_info.i2c_dev.clients[i].client.adapter = < NULL; --- > if (fs455_channel_info.i2c_dev.i2c_registration & 0x01) { > > i2c_del_driver(&fs455_channel_info.i2c_dev.driver); > for (i = 0; i < FS455_MAX_I2C_DEVICES; i++) > fs455_channel_info.i2c_dev.clients[i].client.adapter > = NULL; > > fs455_channel_info.i2c_dev.i2c_registration &= ~(0x01); > fs455_channel_info.enc_device = NULL; > } > return 0; > } > static int isRegAddrValid(unsigned char addr) > { > if(((addr>=0x80)&&(addr<0x8D)) || ((addr>=0xAE)&&(addr<0xC0)) || (addr>0xC4)) > return 0; > else > return 1; > } > static int fs455RegSize(unsigned char addr) > { > if(((addr>=0x44)&&(addr<=0x4E)) || > ((addr>=0x60)&&(addr<=0x6C)) || > ((addr>=0x7E)&&(addr<=0x8D))) > return 1; > else > return 2; > } > static int fs455_setcontrol(enum vid_enc_ctrl_id ctrl, unsigned char val, struct vid_encoder_device *enc) > { > int err = 0; > struct i2c_client *ch_client; > u16 regVal; > unsigned char newState; > unsigned long temp; > int fsvideo = 0; > > if (enc == NULL) { > dev_err(fs455_i2c_dev, "NULL Pointer\n"); > return -EINVAL; > } > > switch (ctrl) { > case VID_ENC_CTRL_MUTE: > if((val<0)||(val>5))return -EINVAL; > newState = muteState; > if(0==val){ > newState &= ~MUTE_USER; > }else if(1==val) { > newState |= MUTE_USER; > }else if(2==val){ > newState &= ~MUTE_ERROR; > }else if(3==val){ > newState |= MUTE_ERROR; > }else if(4==val){ > newState &= ~MUTE_OTHERS; > }else if(5==val){ > newState |= MUTE_OTHERS; > }else{ > return -EINVAL; > } > printk(KERN_INFO "FS455 mute cmd:%d state:(0x%x)->(0x%x).\n", val, muteState, newState); > if((newState && muteState)||((!newState)&&(!muteState))){ > muteState = newState; > return 0; //no need to touch encoder settings. > } > > if(newState){ > temp = davinci_readl(0x01c70400); > temp &= ~0x1; > davinci_writel(temp, 0x01c70400); > printk(KERN_INFO "Mute hsync/vsync signal.\n"); > } > else{ > temp = davinci_readl(0x01c70400); > temp |= 0x1; > davinci_writel(temp, 0x01c70400); > printk(KERN_INFO "Unmute hsync/vsync signal.\n"); > } > > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_VID_CNTL0, ®Val, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_VID_CNTL0 failed (0x%x)\n", err); > return -EINVAL; > } > if(regVal&0x3) > regVal=0x0408; > else{ > regVal=0x0208; > fsvideo = 1; > } > if(!newState){ > regVal &= 0x0608; > err = fs455_i2c_write_reg(ch_client, FS455_PWR_MGNT, regVal, 2); > }else{ > regVal |= 0x0007; > err = fs455_i2c_write_reg(ch_client, FS455_PWR_MGNT, regVal, 2); > } > if(err){ > printk(KERN_INFO "FS455 mute (0x%x)->(0x%x) failed! (0x%x)\n", muteState, newState, err); > //FS455 mode change failed, revert hsync/vsync to original. > if(muteState){ > temp = davinci_readl(0x01c70400); > temp &= ~0x1; > davinci_writel(temp, 0x01c70400); > } > else{ > temp = davinci_readl(0x01c70400); > temp |= 0x1; > davinci_writel(temp, 0x01c70400); > } > }else{ > if(fsvideo == 0) { > //issue soft-reset command to fs455, try to fix sdr376873 > regVal = 0x2001; > fs455_i2c_write_reg(ch_client, FS455_CR, regVal, 2); > printk(KERN_INFO "soft-reset FS455!\n"); > regVal = 0x2000; > fs455_i2c_write_reg(ch_client, FS455_CR, regVal, 2); > } > muteState = newState; > } > break; > case VID_ENC_CTRL_HOFFSET: > printk(KERN_INFO "IHO set: %d\n", val); > regVal = val; > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_write_reg(ch_client, FS455_IHO, regVal, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "IHO set failed (0x%x)\n", err); > return -EINVAL; > } > break; > case VID_ENC_CTRL_VOFFSET: > printk(KERN_INFO "IVO set: %d\n", val); > regVal = val; > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_write_reg(ch_client, FS455_IVO, regVal, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "IVO set failed (0x%x)\n", err); > return -EINVAL; > } > break; > case VID_ENC_CTRL_HSC: > printk(KERN_INFO "HUSC set: %d\n", val); > regVal = (val<<8); > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_write_reg(ch_client, FS455_HSC, regVal, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "HSC set failed (0x%x)\n", err); > return -EINVAL; > } > break; > case VID_ENC_CTRL_FS455TEST: > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > if((val!=1)&&(val!=0)) > return -EINVAL; > > err = fs455_i2c_read_reg(ch_client, FS455_MISC_45, &newState, 1); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_MISC_45 failed (0x%x)\n", err); > return -EINVAL; > } > if(val == 1) > newState |= (val<<1); > else > newState &= !(val<<1); > > printk(KERN_INFO "FS455 ColorBar test %d\n", newState); > err = fs455_i2c_write_reg(ch_client, FS455_MISC_45, newState, 1); > if(err != 0){ > dev_err(fs455_i2c_dev, "FS455_MISC_45 set failed (0x%x)\n", err); > return -EINVAL; > } > break; > case VID_ENC_CTRL_GAIN: > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > if((val>3)&&(val<0)) > return -EINVAL; > > err = fs455_i2c_read_reg(ch_client, FS455_MISC_47, &newState, 1); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_MISC_47 failed (0x%x)\n", err); > return -EINVAL; > } > newState &= ~0x3; > newState |= (val&0x3); > > printk(KERN_INFO "MISC_47 set: 0x%x\n", newState); > err = fs455_i2c_write_reg(ch_client, FS455_MISC_47, newState, 1); > if(err != 0){ > dev_err(fs455_i2c_dev, "FS455_MISC_47 set failed (0x%x)\n", err); > return -EINVAL; > } > break; > case VID_ENC_CTRL_SHP: > printk(KERN_INFO "SHP set: %d\n", val); > regVal = (val&0x1F); > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_write_reg(ch_client, FS455_SHP, regVal, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "SHP set failed (0x%x)\n", err); > return -EINVAL; > } > break; > case VID_ENC_CTRL_FLK: > printk(KERN_INFO "FLK set: %d\n", val); > regVal = (val&0x1F); > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_write_reg(ch_client, FS455_FLK, regVal, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "FLK set failed (0x%x)\n", err); > return -EINVAL; > } > break; > case VID_ENC_CTRL_LUMA: > printk(KERN_INFO "LUMA bandwidth set: %d\n", val); > regVal = val; > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_write_reg(ch_client, FS455_LUMA_BANDWIDTH, regVal, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "FS455_LUMA_BANDWIDTH set failed (0x%x)\n", err); > return -EINVAL; > } > break; > case VID_ENC_CTRL_FS455REGA: > if(isRegAddrValid(val)){ > printk(KERN_INFO "FS455 reg address set to: 0x%x\n", val); > } > else{ > printk(KERN_INFO "FS455 reg address 0x%x is not supported\n", val); > return -EINVAL; > } > fs455RegAddr = val; > break; > case VID_ENC_CTRL_FS455REGH: > fs455RegH = val; > if(fs455RegSize(fs455RegAddr)==2){ > regVal = (fs455RegH<<8)+fs455RegL; > printk(KERN_INFO "FS455 reg 0x%x is set to: 0x%x\n", fs455RegAddr, regVal); > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_write_reg(ch_client, fs455RegAddr, regVal, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "set reg 0x%x failed (0x%x)\n", fs455RegAddr, err); > return -EINVAL; > } > } > break; > case VID_ENC_CTRL_FS455REGL: > fs455RegL = val; > if(fs455RegSize(fs455RegAddr)==1){ > regVal = (fs455RegH<<8)+fs455RegL; > printk(KERN_INFO "FS455 reg 0x%x is set to: 0x%x\n", fs455RegAddr, regVal); > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_write_reg(ch_client, fs455RegAddr, fs455RegL, 1); > if(err != 0){ > dev_err(fs455_i2c_dev, "set reg 0x%x failed (0x%x)\n", fs455RegAddr, err); > return -EINVAL; > } > } > else{ > printk(KERN_INFO "please input higher 8-bits for register 0x%x\n", fs455RegAddr); > } > break; > case VID_ENC_CTRL_BRIGHTNESS: > case VID_ENC_CTRL_CONTRAST: > case VID_ENC_CTRL_HUE: > case VID_ENC_CTRL_SATURATION: > case VID_ENC_CTRL_FS455ID: > err = -EINVAL; > break; > } > return err; > } > static int fs455_getcontrol(enum vid_enc_ctrl_id ctrl, unsigned char *val, struct vid_encoder_device *enc) > { > int err = 0; > struct i2c_client *ch_client; > u16 regVal; > u8 u8val; > unsigned long temp; > > if (enc == NULL) { > dev_err(fs455_i2c_dev, "NULL Pointer\n"); > return -EINVAL; 335c975,1124 < fs455_channel_info.enc_device = NULL; --- > > switch (ctrl) { > case VID_ENC_CTRL_MUTE: > printk(KERN_INFO "FS455 muteState: 0x%x\n", muteState); > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_PWR_MGNT, ®Val, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_PWR_MGNT failed (0x%x)\n", err); > return -EINVAL; > } > printk(KERN_INFO "FS455_PWR_MGNT: 0x%x\n", regVal); > if((regVal&0x0007) && (!muteState)){ > //sync up mute state by unmuting > regVal &= 0x0608; > err = fs455_i2c_write_reg(ch_client, FS455_PWR_MGNT, regVal, 2); > }else if(!(regVal&0x0007) && muteState){ > //sync up mute state by muting > regVal |= 0x0007; > err = fs455_i2c_write_reg(ch_client, FS455_PWR_MGNT, regVal, 2); > } > if(err){ > printk(KERN_INFO "FS455 mute enforcement failed!(0x%x)\n", err); > }else{ > if(muteState){ > temp = davinci_readl(0x01c70400); > temp &= ~0x1; > davinci_writel(temp, 0x01c70400); > } > else{ > temp = davinci_readl(0x01c70400); > temp |= 0x1; > davinci_writel(temp, 0x01c70400); > } > } > *val = (unsigned char)muteState; > break; > case VID_ENC_CTRL_HOFFSET: > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_IHO, ®Val, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_IHO failed (0x%x)\n", err); > return -EINVAL; > } > printk(KERN_INFO "FS455_IHO: 0x%x\n", regVal); > *val = 0; > break; > case VID_ENC_CTRL_VOFFSET: > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_IVO, ®Val, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_IVO failed (0x%x)\n", err); > return -EINVAL; > } > printk(KERN_INFO "FS455_IVO: 0x%x\n", regVal); > *val = 0; > break; > case VID_ENC_CTRL_HSC: > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_HSC, ®Val, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_HSC failed (0x%x)\n", err); > return -EINVAL; > } > printk(KERN_INFO "FS455_HSC: 0x%x\n", regVal); > *val = (regVal>>8); > break; > case VID_ENC_CTRL_FS455REGA: > printk(KERN_INFO "FS455 Reg Dump:\n"); > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > > { > if(fs455RegSize(fs455RegAddr)==2){ > fs455_i2c_read_reg(ch_client, fs455RegAddr, ®Val, 2); > printk(KERN_INFO "fs455 Reg (0x%x) = 0x%x\n", fs455RegAddr, regVal); > } > if(fs455RegSize(fs455RegAddr)==1){ > fs455_i2c_read_reg(ch_client, FS455_MISC_45, &u8val, 1); > printk(KERN_INFO "fs455 Reg (0x%x) = 0x%x\n\n", fs455RegAddr, u8val); > } > fs455_i2c_read_reg(ch_client, FS455_IHO, ®Val, 2); > printk(KERN_INFO "FS455_IHO=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_IVO, ®Val, 2); > printk(KERN_INFO "FS455_IVO=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_IHW, ®Val, 2); > printk(KERN_INFO "FS455_IHW=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_VSC, ®Val, 2); > printk(KERN_INFO "FS455_VSC=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_HSC, ®Val, 2); > printk(KERN_INFO "FS455_HSC=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_CR, ®Val, 2); > printk(KERN_INFO "FS455_CR=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_MISC, ®Val, 2); > printk(KERN_INFO "FS455_MISC=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_PLL_M_PUMP, ®Val, 2); > printk(KERN_INFO "FS455_PLL_M_PUMP=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_PLL_N, ®Val, 2); > printk(KERN_INFO "FS455_PLL_N=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_PLL_PDIV, ®Val, 2); > printk(KERN_INFO "FS455_PLL_PDIV=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_SHP, ®Val, 2); > printk(KERN_INFO "FS455_SHP=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_FLK, ®Val, 2); > printk(KERN_INFO "FS455_FLK=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, 0x40, ®Val, 2); > printk(KERN_INFO "FS455_CHR_FREQ_L=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, 0x42, ®Val, 2); > printk(KERN_INFO "FS455_CHR_FREQ_H=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_MISC_45, &u8val, 1); > printk(KERN_INFO "FS455_MISC_45=0x%x\n", u8val); > > fs455_i2c_read_reg(ch_client, FS455_MISC_46, &u8val, 1); > printk(KERN_INFO "FS455_MISC_46=0x%x\n", u8val); > > fs455_i2c_read_reg(ch_client, FS455_MISC_47, &u8val, 1); > printk(KERN_INFO "FS455_MISC_47=0x%x\n", u8val); > > fs455_i2c_read_reg(ch_client, FS455_HSYNC_WID, &u8val, 1); > printk(KERN_INFO "FS455_HSYNC_WID=0x%x\n", u8val); > > fs455_i2c_read_reg(ch_client, FS455_BURST_WID, &u8val, 1); > printk(KERN_INFO "FS455_BURST_WID=0x%x\n", u8val); > > fs455_i2c_read_reg(ch_client, FS455_BPORCH, &u8val, 1); > printk(KERN_INFO "FS455_BPORCH=0x%x\n", u8val); > > fs455_i2c_read_reg(ch_client, FS455_FR_PORCH, &u8val, 1); > printk(KERN_INFO "FS455_FR_PORCH=0x%x\n", u8val); > > fs455_i2c_read_reg(ch_client, FS455_MISC_74, &u8val, 1); > printk(KERN_INFO "FS455_MISC_74=0x%x\n", u8val); > > fs455_i2c_read_reg(ch_client, FS455_PWR_MGNT, ®Val, 2); > printk(KERN_INFO "FS455_PWR_MGNT=0x%x\n", regVal); > > fs455_i2c_read_reg(ch_client, FS455_LUMA_BANDWIDTH, ®Val, 2); > printk(KERN_INFO "FS455_LUMA_BANDWIDTH=0x%x\n", regVal); 337c1126,1171 < return 0; --- > } > break; > case VID_ENC_CTRL_FS455TEST: > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_MISC_45, &u8val, 1); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_MISC_45 failed (0x%x)\n", err); > return -EINVAL; > } > printk(KERN_INFO "FS455_MISC_45: 0x%x\n", u8val); > *val = (u8val&0x2)? 1 : 0; > break; > case VID_ENC_CTRL_FS455ID: > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_ID, ®Val, 2); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_ID failed (0x%x)\n", err); > return -EINVAL; > } > printk(KERN_INFO "FS455_ID: 0x%x\n", regVal); > if(regVal == 0xFE05) *val = 1; > else *val = 0; > break; > case VID_ENC_CTRL_GAIN: > ch_client = &fs455_channel_info.i2c_dev.clients[FS455].client; > err = fs455_i2c_read_reg(ch_client, FS455_MISC_47, &u8val, 1); > if(err != 0){ > dev_err(fs455_i2c_dev, "Read FS455_MISC_47 failed (0x%x)\n", err); > return -EINVAL; > } > printk(KERN_INFO "FS455_MISC_47: 0x%x\n", u8val); > *val = (regVal&0x3); > break; > case VID_ENC_CTRL_FS455REGH: > case VID_ENC_CTRL_FS455REGL: > case VID_ENC_CTRL_SHP: > case VID_ENC_CTRL_FLK: > case VID_ENC_CTRL_LUMA: > case VID_ENC_CTRL_BRIGHTNESS: > case VID_ENC_CTRL_CONTRAST: > case VID_ENC_CTRL_HUE: > case VID_ENC_CTRL_SATURATION: > err = -EINVAL; > break; > } > return err; 342c1176 < struct vid_encoder_device *enc) --- > struct vid_encoder_device *enc) 347a1182 > u8 u8val; 349c1184 < if ((NULL == enc) || (NULL == mode_info)) { --- > if ((enc == NULL) || (mode_info == NULL)) { 355c1190 < if (NULL == mode) { --- > if (mode == NULL) { 372,373c1207,1208 < (fs455_configuration.output[outindex]. < standards[std_index], mode)) { --- > (fs455_configuration. > output[outindex].standards[std_index], mode)) { 375,376c1210,1211 < fs455_configuration.output[outindex]. < standards[std_index]; --- > fs455_configuration. > output[outindex].standards[std_index]; 382c1217 < || (NULL == mymode)) { --- > || (mymode == NULL)) { 389c1224 < fs455_channel_info.params.mode); --- > fs455_channel_info.params.mode); 393a1229,1230 > if(fs455_component_std_info[std_index][i].reg==(-1)) break; > 396,397d1232 < if (!reg) < break; 404a1240 > //printk(KERN_INFO "Set FS455 reg: 0x%x with 0x%x\n", reg, val); 406,407c1242 < } < while (i < FS455_MAX_REGISTERS); --- > } while (i < FS455_MAX_REGISTERS); 411d1245 < printk("Set standard failed\n"); 417c1251 < printk("Non-Standard Mode not Supported yet\n"); --- > printk(KERN_INFO "Non-Standard Mode not Supported yet\n"); 429c1263 < dev_dbg(fs455_i2c_dev , "%s ::mode_name = %s\n", __FUNCTION__, mode_name); --- > dev_dbg(fs455_i2c_dev, "mode_name = %s\n", mode_name); 432c1266 < mode_name)) { --- > mode_name)) 434c1268 < } --- > 441c1275 < struct vid_encoder_device *enc) --- > struct vid_encoder_device *enc) 445c1279 < if ((NULL == enc) || (NULL == mode_info)) { --- > if ((enc == NULL) || (mode_info == NULL)) { 452,454c1286,1287 < if (NULL == my_mode_info) { < dev_err(fs455_i2c_dev, < "NULL Pointer for current mode info\n"); --- > if (my_mode_info == NULL) { > dev_err(fs455_i2c_dev, "NULL Pointer for current mode info\n"); 462,463c1295,1298 < /* Following function is used to set output format in fs455 device. The index < of the output format is passed as the argument to this function. */ --- > /* > * Following function is used to set output format in fs455 device. The index > * of the output format is passed as the argument to this function. > */ 469c1304 < if ((NULL == enc) || (NULL == output)) { --- > if ((enc == NULL) || (output == NULL)) { 481c1316 < = fs455_configuration.output[0].standards[0]; --- > = fs455_configuration.output[0].standards[0]; 484c1319 < if (NULL == my_mode_info) { --- > if (my_mode_info == NULL) { 503c1338 < if ((NULL == enc) || (NULL == output)) { --- > if ((enc == NULL) || (output == NULL)) { 511,512c1346,1347 < strncpy(output, fs455_configuration.output[0].output_name, < len); --- > > strncpy(output, fs455_configuration.output[0].output_name, len); 519,520c1354,1357 < /* Following function is used to enumerate outputs supported by the driver. < It fills in information about the output in the outp. */ --- > /* > * Following function is used to enumerate outputs supported by the driver. > * It fills in information about the output in the outp. > */ 522c1359 < struct vid_encoder_device *enc) --- > struct vid_encoder_device *enc) 525c1362 < if ((NULL == enc) || (NULL == output)) { --- > if ((enc == NULL) || (output == NULL)) { 530c1367 < if (index >= fs455_configuration.no_of_outputs) { --- > if (index >= fs455_configuration.no_of_outputs) 532c1369 < } --- > 541,542c1378,1379 < struct i2c_driver *driver, < struct i2c_adapter *adap, int addr) --- > struct i2c_driver *driver, > struct i2c_adapter *adap, int addr) 546c1383 < if (client->adapter) { --- > if (client->adapter) 548c1385 < } else { --- > else { 554c1391 < if (err) { --- > if (err) 556d1392 < } 566c1402 < if (!client->adapter) { --- > if (!client->adapter) 568c1404 < } else { --- > else { 577,579c1413,1415 < * Note : It is observed that FS455's initial read call fails and required to < * invoke atleast 2nd Read call,so , Max Read offset moved to 3 < */ --- > * Note : It is observed that FS455's initial read call fails and required to > * invoke atleast 2nd Read call,so , Max Read offset moved to 3 > */ 591,599c1427,1435 < err |= fs455_i2c_attach_client(&fs455_channel_info.i2c_dev. < clients[0].client, < &fs455_channel_info.i2c_dev. < driver, adap, < fs455_channel_info.i2c_dev. < clients[0].i2c_addr); < < /*TBD for comment FS455 SLAVE READ < * Read Valid Slave ID. --- > err |= fs455_i2c_attach_client(&fs455_channel_info.i2c_dev.clients[0]. > client, > &fs455_channel_info.i2c_dev.driver, > adap, > fs455_channel_info.i2c_dev.clients[0]. > i2c_addr); > /* > * TBD for comment FS455 SLAVE READ > * Read Valid Slave ID. 603,604c1439,1442 < chip_id = i2c_smbus_read_word_data(&fs455_channel_info.i2c_dev. < clients[0].client, FS455_ID); --- > chip_id = > i2c_smbus_read_word_data(&fs455_channel_info. > i2c_dev.clients[0].client, > FS455_ID); 608c1446,1447 < dev_err(fs455_i2c_dev , "Failed to Read & Detect FS455\n"); --- > dev_err(fs455_i2c_dev, > "Failed to Read & Detect FS455\n"); 610,611c1449,1451 < } else { < dev_err(fs455_i2c_dev , "Read FS455 Device ID OK as ID=0x%04X\n", --- > } else > dev_err(fs455_i2c_dev, > "Read FS455 Device ID OK as ID=0x%04X\n", 613d1452 < } 637c1476 < printk("Registered FS455LF with Vid Enc Mgr\n");; --- > printk(KERN_INFO "Registered FS455LF with Vid Enc Mgr\n"); 646,649c1485,1491 < i2c_del_driver(&fs455_channel_info.i2c_dev.driver); < for (j = 0; j < FS455_MAX_I2C_DEVICES; j++) { < fs455_channel_info.i2c_dev.clients[j].client.adapter = < NULL; --- > if (fs455_channel_info.i2c_dev.i2c_registration & 0x01) { > i2c_del_driver(&fs455_channel_info.i2c_dev.driver); > for (j = 0; j < FS455_MAX_I2C_DEVICES; j++) > fs455_channel_info.i2c_dev.clients[j].client.adapter > = NULL; > fs455_channel_info.i2c_dev.i2c_registration = 0; > vid_enc_unregister_encoder(&fs455_dev); 651d1492 < vid_enc_unregister_encoder(&fs455_dev); 654d1494 < 657c1497,1498 < --- > MODULE_AUTHOR(DRIVER_AUTHOR); > MODULE_DESCRIPTION(DRIVER_DESC);